Many imaging devices, such as solid state imaging devices including, but not limited to, complementary metal-oxide semiconductor (“CMOS”) devices, charge coupled devices (“CCD”) require the implementation of an analog-to-digital converter (“ADC”). The imaging device typically has one or more pixels, such as a two-dimensional array of pixels, where each pixel generates an analog output signal (the “pixel output signal”) the level of which is not known. The pixel output signal is typically converted, as necessary, into digital data. In a typical imaging device having a pixel array, where the pixel array is a matrix organized in columns and rows, each column typically has associated therewith a column ADC to convert the pixel output signal then active in that given column to digital data.
As is known in the art, in certain imaging devices the pixel output signal, which may be a voltage signal, is typically compared with a ramped reference signal, which also may be a voltage signal. During this comparison, a counter operates to keep track of the number of pulses of a clock signal required for the ramped reference signal to become greater than (or less than, depending on the particular implementation) than the pixel output signal. From the operation of the counter, a digital data signal can be derived.
In certain implementations of the prior art, multiple comparisons of the pixel output signal with the ramped reference signal may be performed to increase the accuracy of the conversion of the analog pixel output signal into digital data. However, performing multiple comparisons typically results in a low frame rate due to the increased amount of time required to perform the multiple comparisons.
Therefore, there is a need for an ADC that increases analog-to-digital conversion performance while minimizing the amount of time required to perform the conversion.